1. Field of the Invention
This invention relates to testing, and more particularly to the design of very large scale integrated ("VLSI") circuit devices so that they can be tested efficiently during several different testing operations.
2. Background Art
VLSI circuit devices, containing thousands of functional circuit elements on a single semiconductor chip, must be tested at several different stages during the manufacturing of the electronic data processing systems made from such devices, so that the correct fabrication of the devices themselves, and of the interconnections between them, may be assured. The first testing operation is performed on an individual device when it has been initially fabricated on a semiconductor wafer. Interconnection and communication between the device and its testing apparatus is achieved by means of a mechanism called a wafer stepper that moves a set of electrical probes above the top surface of the wafer, and causes those probes to achieve simultaneous physical contact with all the input and output terminals of an individual device. This process continues until all devices on the wafer have been contacted and tested. This first testing operation is called wafer (or chip) testing.
After the completion of wafer testing, the individual semiconductor chips are separated from the wafer by a dicing process. Those devices which were classified as functionally good by the wafer testing operation are next assembled in protective packages called modules. Numerous types of module packages exist, and they can be assembled by various bonding and encapsulation processes. Modules may contain one or a plurality of semiconductor chips. Those modules containing one chip are called single-chip modules (SCMs). Those modules containing a plurality of chips are called multichip modules (MCMs).
Modules are subjected to two different types of testing operations. The first of these operations is performed on an individual module package which is connected to its testing apparatus by a pluggable mechanism called a module socket into which the electrical contact pins of the module are secured. This operation is called module testing, and its objectives are to verify the correctness of the module assembly process, and to reverify the continuing functionality of the chip(s) contained in the module.
The second module testing process is performed when it is necessary to enhance the operational reliability of shipped modules, by accelerating and provoking the immediate failure of those correctly but marginally fabricated devices and modules which would otherwise fail early in their expected operational lifespan (e.g., within the first 1000 power-on hours). This is done by exposing the modules to elevated temperature and power-supply voltage stress conditions, and by repeatedly testing the modules under such conditions over an extended time duration (e.g., several hours). This second module testing operation is called burn-in. Since the burn-in operation is a long-duration process requiring special thermal and electrical conditions, it is typically performed simultaneously on groups of functionally identical modules. These modules are secured in module sockets that are permanently mounted on the surface of a specially-designed printed circuit board that is used specifically for this burn-in operation. Electrical access to the input and output terminals of the modules on each burn-in board is normally achieved by means of metal wiring on the top and bottom surfaces of the board, such wiring providing electrical conduction paths from the input and output terminals of each module socket to a connector on the edge of the board, which is connected through the wall of the thermal chamber to the testing apparatus.
The burn-in process is performed by applying the elevated temperature and power-supply voltage conditions required, after which the module test stimulus is applied repetitively to input terminals of the modules mounted on the burn-in boards. For each cycle of repetition, test stimulus is applied to all modules simultaneously and expected test response is monitored for one module only. The modules are monitored in rotation throughout the duration of the burn-in process. A module is said to be undergoing burn-in stress when its inputs are receiving test stimulus but no monitoring of its outputs for expected response is being done. A module is said to be undergoing burn-in testing when its inputs are receiving test stimulus and its outputs are being simultaneously monitored for their expected output response. Alternatively, a modified burn-in process may also be used, wherein only the burn-in stress operation is performed (i.e., burn-in testing is omitted), followed by subsequent reapplication of the module testing operation under conditions of ambient temperature and nominal power supply voltage.
Modules that have successfully passed both the module testing and burn-in operations are then permanently mounted on a printed circuit card or board whose electrical wiring pattern contains the interconnections between such modules so as to realize the function of the desired electronic data processing system or subsystem. Once again, this assembly process must be verified, including the correctness of the wiring interconnections as well as the continued functionality of the constituent modules and semiconductor chips. This card or board testing operation is done in one or both of the following ways: (1) by testing the card or board as a complete functional unit, by connecting the testing apparatus to the input and output terminal edge connections of said card or board; or (2) by retesting the individual constituent modules after they have all been permanently mounted on the card or board assembly, by obtaining physical access to the input and output terminals of each module in succession by means of a suitable fixturing apparatus, and by thereafter reapplying the module test for that module. The first of these operations is called through-the-pins card testing, and the second is called in-circuit or module-in-place card testing.
Each of the wafer, module, and card or board testing operations as previously described place differing but similar requirements on the operation of the circuits on semiconductor devices that directly drive the output terminals of such devices. Each of these circuits, which are called off-chip drivers, supply a logical data value to their output terminal as computed by the internal functional circuits of the semiconductor chip. Such data values are supplied to the corresponding output terminal of a driver circuit only when the control input to that circuit specifies that it should be active or enabled. Alternatively, the control value may specify that the driver circuit should be inhibited or disabled, wherein the circuit is said to be at its high-impedance state and is electrically disconnected from its corresponding output terminal.
During wafer and module testing, and more particularly when such testing is performed using a scan-based testing method such as a level sensitive scan design ("LSSD") testing method, a multiplicity of drivers may switch substantially simultaneously as a consequence of the application of test signal values to the input terminals of the device, and particularly as a consequence of the pulsed activation of either scan clocks or functional system clocks. The resulting switching activity can saturate the local capacity of the on-chip power-supply distribution network when an excessive number of drivers supplied by the same local powering network are caused to switch substantially simultaneously in the same logical direction (e.g., from logical 0 to logical 1). This simultaneous-output-switching event can have an adverse effect on the delivery of power to other circuit elements sharing the same local power-supply network, such as the circuits that receive logical values from the input terminals of the semiconductor chip. These circuits, which are called on-chip receivers or simply receivers, interpret the logical values placed on the input terminals and distribute those values to the internal circuit elements of the chip as needed to realize its operating function.
During a simultaneous-output-switching event, the substantially instantaneous power demand of the switching drivers can cause a shift in the voltage or ground reference values of the local power-supply network, which may therefore cause one or more receivers to incorrectly interpret the logical test stimulus value placed on their input terminals. The incorrect stimulus values distributed by the receivers to the internal circuit elements can thus cause a device output response different from the expected response, even for a correctly-fabricated chip. Therefore, it is desirable to provide a means to control off-chip driver enabling and inhibiting to prevent the occurrence of simultaneous-output-switching events, thereby preventing the improper classification of correctly-fabricated devices as defective devices.
During module testing or burn-in of multichip modules, and more particularly when such testing is performed using a scan-based testing method such as an LSSD testing method, in where the output drivers of two or more chips are interconnected by common wiring, it is possible for the test stimulus to simultaneously activate two or more of such interconnected drivers such that these drivers provide opposing data values at their respective output terminals at the same time. This condition, which is called a driver-contention event, can cause an excessive power-supply current flow through the contending driver circuits that may immediately, or ultimately by repetition, result in the destruction of the driver circuits. Therefore, it is desirable to provide a means to control off-chip driver enabling and inhibiting to prevent the occurrence of driver-contention events, thereby preventing the destruction of correctly-fabricated devices and modules.
During burn-in of single-chip modules or multichip modules, it is desirable to maximize the number of identical module parts that can be simultaneously fitted and exercised in the thermal chamber. Module burn-in boards are therefore designed to maximize the number of module sockets that can be mounted on such boards, and to minimize the complexity of interconnect wiring between such sockets and the board edge connection to the testing apparatus. It is also desirable that the wiring pattern of such boards be suitable to be used for burn-in of different module functional designs characterized by differing uses of the module input and output terminals (e.g., terminal I/0 may be used as an input on module design A and as an output on module design B). These objectives are achieved by establishing common wiring paths on the burn-in board between its edge connection and the corresponding module input or output terminals at each socket location. Module functional input terminals at all socket locations are thus wired in common, permitting the simultaneous application of test input stimulus to all modules during the burn-in stress operation. However, all module output terminals at each socket location are then also identically wired in common, thus precluding the selective monitoring of individual modules as required by the burn-in testing operation. Moreover, although common module input stimulus should result in identical module output response for correctly fabricated modules, the presence of a faulty module (or faulty burn-in board) can produce driver-contention events as previously described, although in this instance between the corresponding driver circuits on separate modules. During the extended duration of the burn-in operation, such occurrences could result in the progressive destruction of all modules occupying the same board. Therefore, it is desirable to provide a means on each module to simultaneously inhibit all driver circuits connected to module terminals, the means being controlled from module input terminals, such terminals at each burn-in board socket location being made separately accessible to the burn-in testing apparatus by means of separate wiring connections between the burn-in board edge connector and the control terminals at each socket location.
During card or board testing operations, similar means for semiconductor device driver control should be provided for prevention of driver-contention events as previously described for multichip module testing and module burn-in operations. To perform through-the-pins card testing without the risk of driver contention, each module should be designed with means to inhibit those off-module drivers whose output terminals are functionally wired in common with the output terminals of other modules, such means being independently controllable so that upon application of test stimulus no more than one driver is ever simultaneously enabled for any common connection between two or more drivers. To perform in-circuit card testing without the risk of driver contention, each module should be designed with means to inhibit those off-module drivers whose output terminals are functionally wired in common with either the input or output terminals of other modules, and such means should be independently controllable for each module during such card testing. Thus, through-the-pins card testing requirements are similar to those of multichip module testing, and in-circuit card testing requirements are similar to those of module burn-in.
FIG. 1 shows a schematic diagram of a level sensitive scan design (LSSD) logic device, frequently used in conjunction with VLSI circuit testing as described herein. LSSD logic devices consist of both combinational logic elements and sequential logic elements. In LSSD, all sequential logic elements are realized as shift register latches (SRLs), which are exemplified in FIG. 1 by Shift Register Latch Sets 1 and 2. The combinational logic elements are exemplified by Combinational Networks 3, 4, and 5, and by AND gates 6 and 7.
In general, testing of LSSD logic devices is accomplished by loading test input stimulus values into Shift Register Latch Sets 1 and 2, by applying test input stimulus to data input terminals S, by pulsed activation of either system clock C1 or system clock C2 (but not both at the same time) to load new data values into either Shift Register Latch Set 1 or 2 respectively, by measurement of output response values on data output terminal R, and by unloading test output response values from Shift Register Latch Sets 1 and 2. Loading of test input stimulus data values into Shift Register Latch Sets 1 and 2 is accomplished by placing a data value on scan input terminal IN, followed by pulsed activation of scan clock A, and then followed by pulsed activation of scan clock B. To complete loading of all SRLs in Shift Register Latch Sets 1 and 2, this scan clock A and B pulse sequence must be repeated with new data values on scan input terminal IN for as many cycles as the total number of SRLs in Shift Register Latch Sets 1 and 2. Unloading of test output response data values from Shift Register Latch Sets 1 and 2 is accomplished in similar fashion by applying a repetition of scan clock A and B pulse pairs, and by measuring the output response on scan output terminal OUT after the application of each pulse pair.
For purposes of describing the preferred embodiment of the present invention, it is convenient to introduce a classification scheme to distinguish four categories of input and output signals that are used during testing. Referring to the LSSD device of FIG. 1, for example, all those inputs that must be manipulated during testing to load logical values into Shift Register Latch Sets 1 and 2 are hereafter called test-function inputs, and are exemplified in FIG. 1 by the input terminals A, B, IN, C1 and C2. All those outputs that must be manipulated during testing to unload logical values from Shift Register Latch Sets 1 and 2 are hereafter called test-function outputs, and are exemplified in FIG. 1 by output terminal OUT. Additionally, output terminals that may be functionally required to selectively transfer test-function input values by combinational logic means to the output terminals of the device--as exemplified in FIG. 1 by output terminal T which can so transfer the value of test-function input terminal C1 by means of AND gate 6--are hereafter also called test-function outputs. All LSSD device inputs other than those previously discussed, as exemplified in FIG. 1 by input terminal S, are hereafter called data inputs. All LSSD device outputs other than those previously discussed, as exemplified by output terminals R1 and R2 in FIG. 1, are hereafter called data outputs.
A prior approach to simultaneous-output-switching event prevention is illustrated in FIGS. 2A and 2B. FIG. 2A shows a single receiver circuit 10 driving two resistive polysilicon delay lines 12, 14 which propagate the input waveform around the periphery of a semiconductor device (not shown), each line traversing two adjacent edges of the device. All driver off-chip circuits 16 are located at the chip periphery, and each is automatically attached to this delay line structure at its point of closest proximity to one of the delay lines 12, 14.
FIG. 2B shows an off-chip driver 16, consisting of driver element 18 and AND gate element 20. Driver element 18 supplies the logic value provided on the System Data input terminal of off-chip driver 16 to its Chip Data Output terminal, only when activated by means of AND gate element 20, which requires that logical 1 signal values be simultaneously present on both the System Enable input terminal and the Test Enable input terminal of off-chip driver 16. When a logical 0 value is present on either the System enable or the Test Enable of off-chip driver 16, then driver element 18 is disabled and is said to be at its high-impedance state, wherein it is electrically disconnected from the Chip Output Terminal of off-chip driver 16. This structure prevents driver-contention events for single-chip modules during burn-in and during in-circuit card testing, provided in the latter case that the functional card design permits the testing apparatus to have separate independent access to the driver inhibit control input terminal of each module. However, the delay provided by delay lines 12, 14, can be much longer than desired, especially where chip size is relatively large, resulting in an excessively long polysilicon line, and where the number of OCDs on the chip is relatively low.
FIG. 3 is a timing diagram of an LSSD tester cycle required to utilize the scheme of FIG. 2 in a relatively large chip. Note particularly that the turn-on and turn-off times of the driver inhibit control input are the dominant factors in the tester cycle time. For VLSI circuit devices, this time is quite long as a consequence of the large time constant of the resistive delay line.
FIG. 4 is an improvement of the scheme shown in FIG. 2, wherein added inverter 30, transistors 32 and low-resistance metal interconnect wiring 34 realize an asymmetric switching behavior, such that the turn-off time of the driver inhibit control is much shorter than the turn-on time. Since this structure is logically identical to that of FIG. 2, but merely exhibits a faster switching response for the turn-off transition, it thus also satisfies the requirements to prevent driver-contention events for single-chip modules during burn-in and during in-circuit card testing, again provided in the latter case that the functional card design permits the testing apparatus to have separate independent access to the driver inhibit control input terminal of each module. However, it offers no improvement to driver inhibit turn-on transition delay.
FIG. 5 is a timing diagram of an LSSD tester cycle, like that of FIG. 3, required to utilize the scheme of FIG. 4. Note that although a significant improvement is realized in comparison to the cycle time shown in FIG. 3, the cycling of the driver inhibit control input is still a dominant factor in the total tester cycle time.
FIG. 6 illustrates yet another alternative approach to driver control that has been used for avoidance of simultaneous-output-switching events in connection with OCDs 16. In this case, the delay function is realized using active circuit elements 40 (instead of the resistive delay lines 12, 14 used in the methods described in FIG. 2 and FIG. 4) formed from internal circuit elements (not shown) that otherwise would have been used for functional system logic. Since the switching response of these elements 40 is both symmetric and faster than those delay line elements previously described, the tester cycle appears essentially as in FIG. 2, but requires shorter turn-on and turn-off times for the driver inhibit control, thereby yielding a reduced cycle time. However, since this delay line is realized only at the expense of circuit elements that otherwise would have been used in the functional chip design, this scheme therefore also tends to result in a plurality of off-chip drivers being operated from a single delay stage. Inasmuch as all drivers connected to a particular stage may therefore be activated simultaneously, the scheme shown in FIG. 6 thus cannot be guaranteed to avoid all simultaneous-output-switching events, and is dependent on the number of driver elements so connected, and on the relative placement of said driver elements with regard to the associated on-chip power-supply network design.
While these prior design and testing methods have individually addressed a particular problem of driver control, and have attempted a specific solution for one or two of the problems associated with the cited testing operations, no previously described method has established a comprehensive driver-control design method that can be successively utilized to satisfy the driver control design requirements for each of the cited testing operations.